The present disclosure relates to a balanced signal processing circuit and an analog-digital conversion circuit.
Electronic apparatuses in recent years are desired to process large-volume digital data at high speed. In addition, the electronic apparatuses are desired to consume low power along with downsizing. In terms of low power consumption, low voltage driving is also desired in order to accept a battery as a power source. Such demands are applied to an analog-digital conversion circuit (hereinafter, simply referred to as “A-D conversion circuit”).
FIG. 7 illustrates a balanced signal processing circuit 701 in related art.
A balanced signal is input to a complete differential amplifier 702 through a first input terminal Vin1 and a second input terminal Vin2, and is amplified in voltage. The balanced signal amplified in voltage by the complete differential amplifier 702 is applied to capacitors C104 and C105 through a first switch 102 and a second switch 103. The first switch 102 and the second switch 103 are controlled to be turned on or off by control signals based on a sampling clock (not illustrated). While the first switch 102 and the second switch 103 are closed (turned on), charge is accumulated in the capacitors C104 and C105. The capacitor C104 holds both end voltage Vs1 between a ground node and an input terminal thereof by charge, and the capacitor C105 holds both end voltage Vs2 between a ground node and an input terminal thereof by charge.
While the first switch 102 and the second switch 103 are opened (turned off), the both end voltage Vs1 of the capacitor C104 and the both end voltage Vs2 of the capacitor C105 are input to a comparator 106. The comparator 106 converts a relative potential difference between the both end voltage Vs1 of the capacitor C104 and the both end voltage Vs2 of the capacitor C105 into a logic signal, and then outputs the logic signal.
Note that the output signal of the comparator 106 may be input to, for example, a successive approximation analog-digital conversion logic circuit. In this case, the balanced signal processing circuit 701 and the successive approximation analog-digital conversion logic circuit configure a successive approximation analog-digital conversion circuit as a whole.